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首页> 外文期刊>IEEE Transactions on Parallel and Distributed Systems >The impact of incorrectly speculated memory operations in a multithreaded architecture
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The impact of incorrectly speculated memory operations in a multithreaded architecture

机译:多线程体系结构中错误推测内存操作的影响

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摘要

The speculated execution of threads in a multithreaded architecture, plus the branch prediction used in each thread execution unit, allows many instructions to be executed speculatively, that is, before it is known whether they actually needed by the program. In this study, we examine how the load instructions executed on what turn out to be incorrectly executed program paths impact the memory system performance. We find that incorrect speculation (wrong execution) on the instruction and thread-level provides an indirect prefetching effect for the later correct execution paths and threads. By continuing to execute the mispredicted load instructions even after the instruction or thread-level control speculation is known to be incorrect, the cache misses observed on the correctly executed paths can be reduced by 16 to 73 percent, with an average reduction of 45 percent. However, we also find that these extra loads can increase the amount of memory traffic and can pollute the cache. We introduce the small, fully associative wrong execution cache (WEC) to eliminate the potential pollution that can be caused by the execution of the mispredicted load instructions. Our simulation results show that the WEC can improve the performance of a concurrent multithreaded architecture up to 18.5 percent on the benchmark programs tested, with an average improvement of 9.7 percent, due to the reductions in the number of cache misses.
机译:多线程体系结构中线程的推测执行,加上每个线程执行单元中使用的分支预测,允许许多指令以推测方式执行,即在知道程序是否真正需要它们之前。在这项研究中,我们研究了在原来被错误执行的程序路径上执行的加载指令如何影响内存系统的性能。我们发现指令和线程级的错误推测(错误执行)会为以后的正确执行路径和线程提供间接的预取效果。即使在已知指令或线程级控制推测不正确之后,通过继续执行错误预测的加载指令,可以将在正确执行的路径上观察到的缓存丢失降低16%至73%,平均降低45%。但是,我们还发现这些额外的负载会增加内存流量,并会污染缓存。我们引入了小型的,完全关联的错误执行缓存(WEC),以消除执行错误的加载指令可能导致的潜在污染。我们的仿真结果表明,由于减少了高速缓存未命中次数,因此WEC可以在测试的基准程序上将并发多线程体系结构的性能提高18.5%,平均提高9.7%。

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