A fast readout algorithm for Cluster Counting/Timing drift chambers on a FPGA board

摘要

A fast readout algorithm for fluster Counting and Timing purposes has been implemented and tested on a Virtex 6 core FPCA board. The algorithm analyses and stores data coming from a Helium based drift tube instrumented by 1 CSPS fADC and represents the outcome of balancing between cluster identification efficiency and high speed performance. The algorithm can be implemented in electronics boards serving multiple fADC channels as an online preprocessing stage for drift chamber signals.