Analysis of multiple cell upset characteristics for logical circuits in radiation environment

摘要

With the design and fabrication of integrated circuits entering the deep submicron and nano-scale era, the possibility of radiation inducing multiple cell upsets (MCU) increases noticeably. Extracting MCU characteristics from the observed upsets can provide useful information for designing hardening strategies and fault injection experiments. This paper reports the analysis of MCU characteristics for logical circuits in radiation environment, using mathematical statistics. MCU feature extraction was extended from storage circuits to logical circuits. Gaussian distribution was proposed, verified and implemented in MCU study to describe the condition when MCU dominates (the number of upsets in single event is mostly larger than 1). In this way, MCU characteristics in logical circuits can be analyzed, including both upsets due to cells and burst upsets due to global resources.