0.25 μm CMOS Gate Array

摘要

Design and fabrication technologies for a 0.25 μm CMOS/SIMOX gate-array LSI (300 k Gate/10 mm square) have been developed. We focused on SOI, especially SIMOX, developing fully-depleted, ultra-thin-film CMOS/SIMOX device technology, high-reliability multilevel (four-level)-interconnection technology, and quarter-micron pattern-fabrication technology. The design technologies yield low-voltage (2.0-1.1 V) operating circuits having extremely low power consumption.