Mapping Systolic Arrays for Matrix Multiplication onto Hardware Platforms

摘要

Systolic arrays speed up scientific computations with inherent parallelization, by exploiting massive data pipeline parallelism. In addition, they include short and problem-size independent signal paths, predictable performance, scalability, and simple design and test. In this paper, a hardware implementation of a linear systolic array for matrix multiplication is investigated. The selected platform is a FPGA (Field Programmable Gate Array) device and the description language used as an entry tool to model hardware architecture is the VHDL (Very High Speed Integrated Circuit Hardware Description Language).