Simulate PLL Performance Through Direct Digital Synthesis

摘要

PHASE-LOCKED loops (PLLs) used in frequency synthesizers are based generally on a voltage-controlled oscillator (VCO). The frequency range of a usable VCO is limited to an octave. The direct-digital-synthesizer (DDS) approach is increasingly popular due to its wider frequency range, high resolution, and because its clock frequency can reach up to 200 MHz. But can a PLL with DDS be locked to a baseband signal even when the signal frequency is a not stable one?