Designing An Ultra-high-speed Multiply-accumulate Structure

摘要

In this article, an ultra-high-speed multiply-accumulate (MAC) structure is proposed. This fused MAC block uses low-voltage-swing (LVS) technique in the utilized carry-save adders and the final adder to improve its speed. Carry-save adders and the final adder are implemented with pass-transistor-based Manchester-carry-chain logic. Sense amplifiers are used in the output nodes to amplify the LVS signals to the standard levels of zero and one. With this technique, we achieved the outstanding clock frequency of 15 GHz for a five-stage pipelined MAC, which is 87.5% higher than the highest speed achieved for a pipelined multiplier in 65 nm technology and above, with the power consumption of 255mW/GHz in 1.2 V voltage supply.