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机译:从系统架构到电路网表的离散时间sigma-delta调制器的自动合成
Department of Electrical Engineering, National Chung-Cheng University, Ming-Hsiung, Chia-Yi, Taiwan;
Department of Computer Science and Information Engineering, National Chung-Cheng University, Ming-Hsiung, Chia-Yi, Taiwan;
Department of Electrical Engineering, National Chung-Cheng University, Ming-Hsiung, Chia-Yi, Taiwan;
Department of Computer Science and Information Engineering, National Chung-Cheng University, Ming-Hsiung, Chia-Yi, Taiwan;
Department of Electrical Engineering, National Chung-Cheng University, Ming-Hsiung, Chia-Yi, Taiwan;
sigma-delta modulator; automated synthesis; behavioral modeling; geometric programming; transistor sizing; op-amp synthesis;
机译:连续时间级联sigma-delta调制器合成的系统方法
机译:SPLiT:一种自动化系统,用于通过多级逻辑实现来合成可靠的时序电路
机译:RSYNC:自动合成可靠多电平电路的系统
机译:合成连续时间级联的Sigma-Delta调制器的系统方法
机译:3微米Sigma-Delta调制器和双模分频器,用于Sigma-Delta调制的小数N频率合成。
机译:TMR传感器的Sigma-Delta调制器接口电路的谐波失真优化
机译:电路误差和混合连续/离散时间Sigma-Delta调制器的影响