SOLiT: An automated system for synthesising reliable sequential circuits with multilevel logic implementation

摘要

The paper presents SOLiT, an automated system for synthesising reliable sequential circuits with multilevel logic implementation. The reliability enhancement is achieved by using concurrent error detection scheme with coding techniques. The system receives the behavioural description of finite-state machines, determines the required checker circuits, and generates the physical layouts. The synthesised circuits can detect multiple unidirectional errors. A novel output partitioning algorithm is presented to reduce the hardware cost of the required checker circuits. Results show that the overhead for reliability enhancement of the synthesised sequential circuits is relatively low.