SLIM-ADC: Spin-based Logic-In-Memory Analog to Digital Converter leveraging SHE-enabled Domain Wall Motion devices

摘要

This paper devises a novel Analog to Digital Converter (ADC) framework for energy-aware acquisition of analog signals with Logic-in-Memory capabilities. The beyond-CMOS hardware architecture has been designed to minimize the overall cost of signal acquisition. Spin-Hall Effect driven Domain Wall Motion (SHE-DWM) devices are utilized to realize the proposed framework called Spin-based Logic-In-Memory ADC (SLIM-ADC). Our simulation results indicate that the proposed SLIM-ADC offers similar to 200 fJ energy consumption on average for each analog conversion or logic operation with up to 1 GHz speed. Furthermore, our results indicate that the proposed SLIM-ADC outperforms other state of the art spin-based ADC designs by offering similar to 5.45 mW improved power dissipation on average. Additionally, a Majority Gate (MG)-based Full-Adder (MG-FA) is implemented using the proposed SLIM-ADC. Our results show that the proposed MG-FA offers similar to 2.9-fold reduced power dissipation on average and similar to 1.7-fold reduced delay on average compared to the state of the art Full-Adder designs reported herein.