Proactive correction coset decoding scheme based on SEC-DED code for multibit asymmetric errors in STT-MRAM

摘要

As one promising candidate of next generation nonvolatile memory technologies, spin-transfer torque random access memory (STT-MRAM) offers many attractive characteristics, such as high speed, nonvolatility, high integration density, and excellent CMOS process compatibility. However, the performance and reliability of STT-RAM cells are greatly affected by device operating uncertainties and external circuit variation. As a result, write operations of STT-MRAM are not identical, which introduces asymmetric write failure rates for 0 - 1 and 1 - 0 bit flipping. Error correcting codes (ECCs) are general solutions for protecting memories from errors. The ECCs most widely used in memory technology are the single error correction and double error detection (SEC-DED) codes. Unfortunately, existing SEC-DED code schemes have limited correction capabilities and do not take the different error rates of memories into consideration. Regarding the failure characteristics (e.g., multibit and asymmetric) of STT-MRAM, conventional SEC-DED codes are not efficiently applicable. In this paper, we propose a proactive correction coset decoding scheme to correct double asymmetric errors for STT-MRAM. The scheme is partitioned into two levels: the proactive correction level (PCL) and the asymmetric correction level (ACL). The PCL proactively handles the single-bit error correction and the ACL analyzes the result from the prior level and corrects the second error. These levels are all based on the same standard coset array. Finally, simulation results with an SEC-DED code show the effectiveness and improvement of the proposed decoding scheme.