基于FPGA的IRIG-B（DC）码的解码方案的设计与实现

摘要

IRIG-B code is an universal format of time code in the world and is widely used in timing systems. According to the characteristics of IRIG-B code modulation, a decoding plan based on FPGA is introduced with emphases on how to extract the synchronous second signal accurately from the synchronous timing sequency and how to get the time information included in the B code. The whole project is designed by using Verilog HDL and has been implemented successfully with the results shown.%IRIG-B码是国际上通用的时间码格式，广泛应用于各种系统的时间同步。针对IRIG-B（DC）码的调制特性，介绍一种基于FPGA的B码解调方案。重点描述了如何在同步时序中准确提取秒同步信号并解调B码中包含的时间信息。整个方案中采用Verilog HDL语言进行设计，已成功实现，并给出了验证结果。