Error Correction Coding with NMOS Microprocessors:Volume II. A 6800-Based 7, 3Reed-Solomon Decoder.

摘要

Design, operation and testing of a table-look-up microprocessor-based (Motorola MC6800) (7,3) Reed-Solomon decoder is presented. Decoder operation is fully illustrated by the use of error and erasure pattern examples. Exhaustive (complete) and random (Monte Carlo) testing is employed to exercise the decoder. Test results are analyzed and conclusions drawn relative to decoder performance. (Author)