Etch, Deposition, Cleaning, and Materials Challenges Line the Road to 45 nm

摘要

This issue's Hot Button examines the role played by inter-connect-related issues on the road to the 45-nm technology node. We've assembled some intriguing comments made during a recent panel discussion that shed some light on what lies ahead in the areas of low-k materials, copper PVD/ALD and CMP, electroplating, etch, and cleaning. Applied Materials hosted the panel, titled "The New Reality: Breaking Through to 45 nm," at the International Interconnect Technology Conference held in Burlingame, CA, in early June. Moderator Mark Pinto, senior vice president of Applied's new business and new product group, started the event with an overview of the key challenges facing back-end-of-line (BEOL) integration as the industry moves down the technology curve. Pinto's concluding slide depicted some of the daunting integration obstacles looming in the path to 45-nm yield maximization, such as poor inter-layer and copper adhesion, tensile stress, thermal instability, weak cohesion, low modulus and hardness, and poor via etch selectivity.