FEOL PROCESSING: Strained-silicon engineering leads field of transistor technology improvements

摘要

The implementation of strain engineering has brought to bear a whole new set of techniques for scaling front-end-of-line (FEOL) structures well into and possibly beyond the 45-nm realm. By slightly modifying dielectric films and combining temperature, pressure, and other knob-twisting on the process chambers of existing equipment platforms, the desired film stresses-both compressive and tensile-can be tuned. With what appears to be additive effects, strain engineering boosts electron mobility without narrowing the transistor channel. A number of strain combinations (tensile and compressive SiN, selective epitaxial SiGe, etc.), which vary depending on the process integration schemes of the respective companies, are already in use in many leading-edge fabs. This issue's Hot Button presents the viewpoints of three FEOL gurus, who explain why strain is a great way to manage stress and improve device performance.