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Electrical characterization of 6H-SiC grown by physical vapor transport method

机译:物理气相传输法生长的6H-SiC的电学表征

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摘要

Deep level transient spectroscopy (DLTS) and capacitance versus voltage (C-V) measurements have been used to study the electrical properties of electron traps in n-type 6H-silicon carbide (SiC) grown by physical vapor transport (PVT) technique, designed as Schottky diodes. Ir Schottky- and Ni ohmic-contacts were deposited by sputtering. Current versus voltage (I-V) measurements showed that sputter deposition of the Schottky contact yields diodes with a reduced barrier height and poor rectification characteristics. Four main electron traps revealed in DLTS spectra have activation energies at 0. 39,0.41,0,66, and 0.74 eV below the conduction band. Based on a comparison made with electron traps reported in the literature, we conclude that three of them are well-known traps found in the as-grown or irradiated material. There was no emission signature in the literature to make such a correspondence for the trap at 0.74 eV. Strongly nonhomogenous spatial distribution with a tendency of the trap to accumulation at the surface was found by DLTS and C-V profiling. This together with the fact that the trap at 0.74eV has not been previously reported in as-grown or processed material makes it possible that the trap is sputter deposition induced defect.
机译:深层瞬态光谱法(DLTS)和电容对电压(CV)测量已用于研究通过物理气相传输(PVT)技术生长的n型6H碳化硅(SiC)中电子陷阱的电性能,该技术设计为肖特基二极管。 Ir肖特基和Ni欧姆接触通过溅射沉积。电流与电压(I-V)的测量结果表明,肖特基接触的溅射沉积产生的二极管势垒高度降低且整流特性较差。 DLTS光谱中揭示的四个主要电子陷阱的激活能分别在导带以下0. 39、0.41,0、66和0.74 eV。根据与文献报道的电子陷阱进行的比较,我们得出结论,其中三个是在生长或辐照的材料中发现的众所周知的陷阱。对于0.74 eV处的陷阱,文献中没有发射标记可以做出这样的对应。通过DLTS和C-V轮廓分析发现了强烈的不均匀空间分布,具有陷阱在表面积累的趋势。这与以前没有在生长或加工过的材料中报道过0.74eV陷阱有关的事实,使得该陷阱有可能是溅射沉积引起的缺陷。

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  • 来源
    《Materials Science and Engineering》 |2009年第2期|23-27|共5页
  • 作者单位

    Institute of Electron Technology, Department of Analysis of Semiconductor Nanostructures, Al. Lotnikow 32/46.02-668 Warsaw, Poland;

    Institute of Electron Technology, Department of Analysis of Semiconductor Nanostructures, Al. Lotnikow 32/46.02-668 Warsaw, Poland;

    Institute of Electron Technology, Department of Analysis of Semiconductor Nanostructures, Al. Lotnikow 32/46.02-668 Warsaw, Poland;

    Institute of Electron Technology, Department of Semiconductor Processing for Photonics, Al. Lotnikow 32/46, 02-668 Warsaw, Poland;

    Institute of Physics, Polish Academy of Sciences, Al. Lotnikow 32/46, 02-668 Warsaw, Poland Institute of Electronic Materials Technology, ul. Wolczynska 133, 01 -919 Warsaw. Poland;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    deep level defects; DLTS; silicon carbide;

    机译:深层缺陷;DLTS;碳化硅;

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