Optimal Structural Design of Multi Chip Package to Reduce The Failure in Substrate

摘要

In this study, epoxy molded multi chip package was investigated and a highly reliable structure against failure of copper trace on PCB substrate was proposed. Function failure caused by the pattern crack during component level thermal cycle test was considered. In-plane and out-of-plane movements of package during thermal loading were measured by moire interferometry and shadow moire. Measured data were compared with numerical analysis results. Two dimensional and three dimensional numerical analysis were performed considering visco-elastic material properties. Tensile stress in the core layer was analyzed quantitatively and qualitatively. Analysis showed that the reliability of pattern crack could be improved by decreasing the chip thickness and increasing the core thickness, and that the material property of die adhesive was important.