4kbps Digital BPSK Demodulator - A Proto Type Design, Simulation and Testing

摘要

In order to cater to the future requirement of uplinking large number of commands in IRS mission like CARTOSAT-2, a 4kbps telecommand system has been developed. The onboard baseband system comprises a BPSK demodulator followed by a BCH decoder. This demodulator is fully digital except for a small front end, which is analogue. The heart of the demodulator is the digital phase locked loop (DPLL). This paper presents design, simulation, implementation and test results of the developmental model. The digital implementation allows programmability, repeatability and reliability. The demodulator is implemented using two ACTEL 1280 FPGA's. The acquisition time ranges from 0.75 to 1.75ms. The Bit Error Rate (BER) performance is 10~(-5) for energy per bit to noise density ratio (E_b/N_0) of 10.5 dB.