Design of 12-Bit Σ-Δ ADC with PGA and Programmable Comb Filter

摘要

This paper presents the implementation of 2nd order Σ-Δ ADC with PGA and programmable comb filter. The PGA has a digitally programmable range of I to 128 in binary steps to accommodate a wide range of signal inputs. The PGA implementation is done within the modulator by changing the sampling frequency and ref. capacitor. The three-stage comb filter notch frequency is programmable from 24Hz to 976Hz, which allows various input bandwidths. The design details are presented. The circuit operates on ±5V supply. With an over sampling ratio of 128 and a clock rate of 62.5kHz, the ADC achieves 12 bits (min.) resolution. This work has been done for VSSC under a project Software Programmable Data Acquisition System (SOFTDAS). The chip is functional and measured device results are given.