Utilization of Pipeline Technique in AOP Based Multipliers with Parallel Inputs

摘要

Heretofore many All-One-Polynomials (AOP) based multipliers are proposed over GF(2 m ). Previously proposed multipliers have serial input structure and also suffer from a long critical path delay. In this paper we improve AOP based multipliers by reducing the critical path delay and changing the input structure to parallel. Initially, we modify the wiring of the previously proposed AOP based multipliers. This approach reduces the critical path delay from O(m) to O(log m). In order to further reduce this delay from O(log m) to O(1) the pipeline technique is utilized. The efficiency of the proposed architectures is evaluated based on criteria of time (latency, critical path) and space complexity (gate-latch number).