Design of High Speed Low Power Counter using Pipelining

摘要

We present high-speed scalable counter architectures for high operating frequencies. The design methodology implemented in a 16 bit counter architecture uses basic module and subsequent modules for count generation. The triggering pulses for a subsequent module is generated from state transitions of basic module and preceding subsequent modules using State Exciting Logic (SEL) in case of synchronous operation where clock pulses trigger all the modules simultaneously. As an extension, we connected the modules in asynchronous mode where the most significant bit (MSB) of module/stage is used as clock pulse for the immediate succeeding module. The novelty of the design is the realization of all subsequent modules with equal number of gates, which maintain uniform setup time for all the D Flip Flops (FFs) in the module. And, thus the D FFs when triggered by clock pulse gives uniform output. The proposed counter is designed using VHDL code and simulated using Altera Quartus Ⅱ EP1C20F400C7 device. Analysis reveals that the power dissipation of our proposed counter is 80.47 mW and 80.46 mW with delay parameter of 9.097 ns and 22.476 ns for synchronous and asynchronous connection respectively at 250 MHz.