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首页> 外文期刊>Journal of materials science >Impact of interfacial charges on analog and RF performance of Mg_2Si source heterojunction double-gate tunnel field effect transistor
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Impact of interfacial charges on analog and RF performance of Mg_2Si source heterojunction double-gate tunnel field effect transistor

机译:界面电荷对MG_2SI源异质结双栅极隧道场效应晶体管的模拟和RF性能的影响

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摘要

Tunnel field effect transistors (TFETs) have proved themselves as a better choice for the replacement of MOSFET due to provision of scalability and possibility of better realization of goal to achieve subthreshold swing less than 60 mV/dec-ade. Challenge of lower ON current in conventional TFET has been overcome by a heterojunction double-gate (DG) TFET structure in which a low bandgap material, magnesium silicide (Mg_2Si) is implemented as source region. There is dire need to determine the reliability of such device under various constraints to optimize them for low-power and high-speed applications. Therefore, in this paper, authors examine the device reliability by investigating the analog/RF performance of Mg_2Si source heterojunction double-gate TFET (MSH-DG-TFET) under the influence of interface trap charge polarity and density. This reliability analysis is accomplished by including the effect of trap charges (both positive interface charges, i.e., donors and negative interface charges, i.e., acceptors) at Si/SiO_2 interface. Presence of these trapped acceptor and donor charges at Si/ SiO_2 interface modifies the flat-band voltage which in turn alters the performance of the device. It is revealed that for positive trap charge density of 1 × 10~(12) cm~(-2), the leakage current or off-state current of MSH-DG-TFET drastically increases from an order of 10~(-18) to 10~(-14) A/μm, thus degrading the performance. Further, presence of negative trap charges at interface tends to enhance the flat-band voltage that translates to the higher gate bias to turn the device ON. Results reveal that impact of positive interface charges is more pernicious on the device performance as compared to the negative interface charges. Thus, MSH-DG-TFET is susceptible to the donor traps existing at Si/ SiO_2 in comparison with the acceptor traps. Studies carried out may prove to be very useful for future research work in suggesting better TFET structures comprising of Mg_2Si as source.
机译:由于提供可扩展性和更好地实现目标的可能性,因此证明了隧道场效应晶体管(TFET)作为更换MOSFET的更好的选择,以便实现小于60 mV / DEC-ADE小于60 mV / DEC-ADE的亚阈值摆幅。通过常规TFET在常规TFET中较低的电流挑战已经通过异质结双栅极(DG)TFET结构克服,其中低带隙材料,硅化镁(MG_2SI)被实现为源区。需要急需确定各种约束下这种设备的可靠性,以优化它们的低功耗和高速应用。因此,在本文中,作者通过在接口捕集电荷极性和密度的影响下研究MG_2SI源异质结双栅TFET(MSH-DG-TFET)的模拟/射频性能来检查器件可靠性。通过在SI / SiO_2接口处包括陷阱费用的效果(正面界面费用,即捐赠者和负接口费用,即受体)来实现这种可靠性分析。 Si / SiO_2接口的这些被捕获的受体和供体电荷的存在改变了又改变了器件的平频带电压。据透露,对于1×10〜(12)cm〜(-2)的正捕集电荷密度,MSH-DG-TFET的漏电流或截止状态电流从10〜(-18)的顺序大大增加至10〜( - 14)A /μm,从而降低性能。此外,接口处的负阱电荷的存在趋于增强转换到更高栅极偏置的平坦带电压以打开设备。结果表明,与负接口费相比,阳性接口费用对设备性能的影响更加有害。因此,与受体陷阱相比,MSH-DG-TFET易于在Si / SiO_2处存在的供体陷阱。进行的研究可能证明对于未来的研究工作来说是非常有用的,在提出将MG_2SI作为源的更好的TFET结构。

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  • 来源
    《Journal of materials science》 |2021年第19期|23863-23879|共17页
  • 作者单位

    Chitkara University School of Engineering and Technology Chitkara University Baddi Himachal Pradesh India;

    VLSI Centre of Excellence Chitkara University Institute of Engineering and Technology Chitkara University Rajpura Punjab India;

    VLSI Centre of Excellence Chitkara University Institute of Engineering and Technology Chitkara University Rajpura Punjab India;

    VLSI Centre of Excellence Chitkara University Institute of Engineering and Technology Chitkara University Rajpura Punjab India;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
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