製品開発における設計情報の往還運動解析と実証研究半導体設計開発への適用

摘要

Recent larger and more complicated products involve a great deal of engineering design processes where many iterations among various engineering tasks are often observed. The Dependency Structured Matrix is very useful for identifying where iterations take place, and the pair-wise comparison matrix (PCM) can show which portions of the design problems require much time during the iteration process. This paper discusses iteration models used in engineering design processes and attempts to predict the convergence of iterations within a design project and design problems' features using a PCM. This model is applied to a semiconductor project for the development process of the networking processors to illustrate the model's utility in describing the primary features of an actual design process. The findings are confirmed by eigenvalues and eigenvectors computed using a PCM, which enabled the identification of two dominant features and related tasks weighted with elements in eigenvectors. The impact for cost and scheduling over the actual design process can be found as the result of the dominant features, which include iteration in between logic design and its verification, and also in between physical implementation and its verification. Two models built with replaced tasks are simulated, and the results are found to be improved. Semiconductor hardware IP (intellectual property) replaced based on this method has been confirmed to have an improved impact over the actual design process. The managerial practice and theory are discussed, and suggestions for further research are provided.%エレクトロニクス・システムが大規模化，複雑化する中で，半導体設計開発には価格対性能比の向上と設計開発期間の低 減が求められている．しかし，半導体設計の現場では，手戻り修正作業やタスク（task）間の設計情報の反復工程といった往還運動（iteration）による設計負荷（design impact）が，プロジェクトのコストの増大とスケジュールの長期化を引き起こし，経営上大きな影響を及ぼす問題となっている．本稿ではまずタスク間で生じる設計情報の往還運動に注視して設計工程をモデリングし，往還運動によって生じる負荷問題を経営工学的立場から浮き彫りにする．次にその研究法を半導体設計開発に適用し，設計負荷を低減するための解決策について検討する．