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机译:64位MISTY1块密码的架构和FPGA实现
VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, Patras, Greece;
MISTY1; block cipher; cryptography; NESSIE; inner pipeline; negative edgetriggered register; FPGA;
机译:MISTY1块密码的ASIC实现的紧凑体系结构
机译:MISTY1块密码的区域有效的硬件架构
机译:PRESENT分组密码的硬件架构及其FPGA实现
机译:基于RAM的FPGA实现64位Misty1块密码
机译:具有并发错误检测功能的分组密码的紧凑硬件实现
机译:SIMON轻量级块密码的FPGA建模和优化
机译:64位mIsTY1分组密码的体系结构和FpGa实现