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Architectures and FPGA Implementations of the 64-bit MISTY1 Block Cipher

机译：64位mIsTY1分组密码的体系结构和FpGa实现

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P. Kitsos; M. D. Galanis; O. Koufopavlou;
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1. ARCHITECTURES AND FPGA IMPLEMENTATIONS OF THE 64-BIT MISTY1 BLOCK CIPHER [J] . P. KITSOS, M. D. GALANIS, O. KOUFOPAVLOU Journal of Circuits, Systems, and Computers . 2006,第6期

机译：64位MISTY1块密码的架构和FPGA实现
2. Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher [J] . Dai YAMAMOTO, Jun YAJIMA, Kouichi ITOH IEICE Transactions on fundamentals of electronics, communications & computer sciences . 2010,第1期

机译：MISTY1块密码的ASIC实现的紧凑体系结构
3. Hardware architectures for PRESENT block cipher and their FPGA implementations [J] . Pandey Jai Gopal, Goel Tarun, Karmakar Abhijit Circuits, Devices & Systems, IET . 2019,第7期

机译：PRESENT分组密码的硬件架构及其FPGA实现
4. A RAM-Based FPGA Implementation of the 64-bit MISTY1 Block Cipher [C] . P. Kitsos, M. D. Galanis, O. Koufopavlou IEEE International Symposium on Circuits and Systems . 2005

机译：基于RAM的FPGA实现64位Misty1块密码
5. Compact hardware implementation of block ciphers with concurrent error detection [D] . Cheng, Huiju 2007

机译：具有并发错误检测功能的分组密码的紧凑硬件实现
6. FPGA Modeling and Optimization of a SIMON Lightweight Block Cipher [O] . Sa’ed Abed, Reem Jaffal, Bassam Jamil Mohd, 2019

机译：SIMON轻量级块密码的FPGA建模和优化
7. Efficient FPGA implementation of block cipher MISTY1 [O] . Rouvroy G., Standaert François-Xavier, Quisquater Jean-Jacques, 2003

机译：块密码MISTY1的高效FPGA实现

Architectures and FPGA Implementations of the 64-bit MISTY1 Block Cipher

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