Modified Operand Decomposition Multiplication for High Performance Parallel Multipliers

摘要

A low power operand decomposition multiplication architecture implementation is modified to further reduce its power dissipation and delay. First, the multiplier's implementation was modified to generate the partial products using NAND gates instead of AND and OR gates in order to reduce the number of transistors (area utilized) and to reduce the delay. Then, new types of adders and (4: 2) compressors, that accept negatively weighted bits are used to reduce the number of inverters. Therefore, the resulting multiplier architecture reduces the number of transistors significantly. These modifications result in 20% and 36% reduction in power consumption and energy delay product (EDP), respectively.