Characterization of defect evolution in ultrathin SiO_2 layers under applied electrical stress

摘要

The structural evolution of ultrathin dielectric SiO_2 layers within a Co-silicide/poly-Si/SiO_2/Si multilayer system was studied by in situ transmission electron microscopy (TEM). The interface structure represents a model system for field effect transistors with a SiO_2 dielectric layer. Electrical bias was applied across the interfaces of cross sectional TEM samples using a scanning tunneling microscopy (STM) tip. Atomic structure modifications of the dielectric layer due to the applied electrical field were observed by this in situ STM-TEM technique. Constant bias (+5.0 V) and ramped bias (+3.0 to +10.5 V) stresses applied to the CoSi_2 gate electrode resulted in a loss in capacitance of the dielectric layer consistent with descriptions of soft dielectric breakdown (SBD) and hard dielectric breakdown (HBD). It was found that SBD events are characterized by fluctuations within uniform current step increase of 21 nA and increased roughness of the SiO_2 film due to oxygen vacancy percolation. HBD, however, was found to be preceded by multiple SBD events between +6.5 V and +10 V, cobalt atom migration into the dielectric layer, partial crystallization of the amorphous gate dielectric (dielectric breakdown induced epitaxy), and significant diffusion of oxygen from the SiO_2 layer into the silicon substrate through a reduction-oxidation reaction of the Si/SiO_2 interface. Experimental results demonstrate the feasibility of in situ STM-TEM experiments for studying time-dependent dielectric breakdown behaviors to obtain a direct correlation of individual defect structures and their corresponding electrical signatures. Experimental limitations of this new technique are critically discussed.