Memristor based high speed and low power consumption memory design using deep search method

摘要

The demand for low-power devices in today's world is increasing, and the reason behind this is scaling CMOS technology. Due to scaling, the size of the chip decreases and the number of transistors in System-On-Chip increases. However, transistor miniaturization also introduces many new challenges in circuit design for very large scale integrated circuits. Therefore in this work is introduced a memristor based memory design, the memristor breaks the scaling limitations of CMOS technology and prevails over emerging semiconductor devices. The memristor is forced to the Nano scale design of the invention, and successful fabrication begins to take into account the range of conventional metal oxide semiconductor field effect transistors or more specifically the use of transistors as a whole. The memristor has a history mechanism that allows the memory operation to be combined with the inherent bipolar resistance switching characteristics. Different types of existing mathematical models have been derived from shapes that can be further implemented and tested in a prototype with some crucial parameters thus determined and how they differ from conventional transistor-based designs for a suitable circuit memristor. In this work, low-power complementary metal oxide semiconductor (CMOS) flip-flops have been proposed with deep search pattern method and some key parameters such as delay, power, gate count and other memristor calculations are carried out. The simulations are carried out using Verilog-analog mixed signal. The proposed system is considered as potential devices for building memories because they are very dense, non-volatile scalable devices with faster switching times and low power dissipation and are also compatible with the existing CMOS-technology.