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首页> 外文期刊>Japanese journal of applied physics >Fabrication of thin body InAs-on-insulator structures by Smart Cut method with H~+ implantation at room temperature
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Fabrication of thin body InAs-on-insulator structures by Smart Cut method with H~+ implantation at room temperature

机译:室温下H〜+注入的Smart Cut法制备绝缘体上InAs薄结构

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摘要

This paper demonstrates the fabrication of InAs-on-insulator (InAs-OI) structures with high crystallinity using the Smart Cut process, which combinates direct wafer bonding with a wafer splitting process by implanted H+. Controlling the implantation dose and rate allows us to produce wafer-level InAs-OI structures on Si substrates by H+ implantation at room temperature, which can be performed in standard implantation equipment. It is found that (111) InAs-OI has a much flatter surface after splitting than (100) one. After thinning by using CMP and wet etching, 15 nm thick InAs-OI structures are realized with the high thickness uniformity. (C) 2019 The Japan Society of Applied Physics
机译:本文演示了使用Smart Cut工艺制造的具有高结晶度的InAs-on-insulator(InAs-OI)结构,该工艺将直接晶片键合与通过注入H +的晶片分裂工艺相结合。通过控制注入剂量和注入速率,我们可以在室温下通过H +注入在Si衬底上生产晶圆级InAs-OI结构,该工艺可以在标准注入设备中进行。发现(111)InAs-OI在分裂后具有比(100)In平坦的表面。在通过CMP薄化和湿蚀刻之后,实现了具有高厚度均匀性的15nm厚的InAs-OI结构。 (C)2019日本应用物理学会

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  • 来源
    《Japanese journal of applied physics》 |2019年第sb期|SBBA03.1-SBBA03.6|共6页
  • 作者单位

    Univ Tokyo, Sch Engn, Dept Elect Engn & Informat Syst, Bunkyo Ku, Tokyo 1138656, Japan;

    Univ Tokyo, Sch Engn, Dept Elect Engn & Informat Syst, Bunkyo Ku, Tokyo 1138656, Japan;

    Univ Tokyo, Sch Engn, Dept Elect Engn & Informat Syst, Bunkyo Ku, Tokyo 1138656, Japan;

    Univ Tokyo, Sch Engn, Dept Elect Engn & Informat Syst, Bunkyo Ku, Tokyo 1138656, Japan;

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