Radiation hardness evaluations of 65 nm fully depleted silicon on insulator and bulk processes by measuring single event transient pulse widths and single event upset rates

摘要

We measure single event transient (SET) pulse widths on inverter chains and single event upset (SEU) rates on flip-flops (FFs) fabricated in 65nm fully depleted silicon on insulator (FD-SOI) and bulk processes. The layout designs of test chips are strictly identical between their processes besides buried oxide (BOX) layers. Experimental results show that neutron-induced SEU and SET rates in the FD-SOI process are 230x and 450x lower than those in the bulk process, respectively. (C) 2015 The Japan Society of Applied Physics