A Unified Procedure to Overcome the Byzantine General's Problem for Inter-gate and Intra-gate Bridging Faults in CMOS Circuits

摘要

In this paper, we present two algorithms, which can be used to overcome the Byzantine General's problem for bridging faults during the fault simulation and test pattern generation. The first algorithm applies to hard short bridging faults, and the other applies to resistive bridging faults. These algorithms apply to inter-gate and intra-gate bridging fault. By using these propose algorithms, the usual comparison between the intermediate potential and the logic threshold of the driven gates is replaced by the comparison between the equivalent resistance of the pull-up and pull-down conducting transistors. Moreover, the algorithm is much faster since no spice simulation is required. The accuracy is of ±0.01 V to compare with SPICE simulation for hard short bridging fault and ±0.2 V for resistive bridging fault in the interval of intermediate voltage.