Development of fault-tolerant reduced device version with switched-capacitor based multilevel inverter topologies

摘要

Recently, multilevel inverters (MLIs) are gaining notable importance due to their noteworthy features of "reduced voltage stress" and "total harmonic distortion (THD)." Though MLIs provide a handy solution for renewable energy integration, yet increased numbers of power switches are a major concern for circuit reliability. The reliability can be enhanced with circuit implementation such as reduced device counts (RD) that have fault-tolerant (FT) feature. This article therefore intends to propose two numbers of "modified MLI topologies" configured around "reduced device counts" implementation (RD-MLIs) with the added feature of FT. The proposed topologies in the article are modification over single-phase T-Type RD-MLI. The "modified T-Type topologies" are FT against open circuit fault (OCF) and capable of achieving inherent self-voltage-balance in DC-Link capacitors. The proposed topologies in this article are analyzed for their healthy, faulty, and post fault operation in MATLAB/Simulink environment and a hardware prototype is developed to validate the efficacy of concept and control strategy experimentally. The control strategy is developed as the Simulink model, which is interfaced with dSPACE DS-1104 for generating control pulses to drive switches of modified MLI topologies. The experimental results on proposed "modified single-phase fault-tolerant MLI topologies" validate FT feature against OCF. In essence, the modified topologies offer benefits of having fewer number of diodes, power switches, DC sources, capacitors, drivers and total blocking voltage (TBV in per unit) in comparison to similar other equivalent MLI topologies reported in the literature.