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Realisation of 3GPP-LTE physical downlink data channel with diversity techniques using PlanAhead tool and Virtex device

机译:使用PlanAhead工具和Virtex设备通过分集技术实现3GPP-LTE物理下行链路数据信道

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摘要

A combined architecture of Long Term Evolution (LTE) downlink data channels with optimised transmitter and receiver is proposed in this paper. This work mainly focuses on the downlink physical channels namely Physical Downlink Shared Channel (PDSCH), Physical Broadcast Channel (PBCH) and Physical Multicast Channel (PMCH) in Single Input Single Output (SISO), Multiple Input Single Output (MISO) and Multiple Input Multiple Output (MIMO) configurations. The data from higher layer are scrambled, modulated, layer mapped, precoded and mapped to resource elements in the transmitter. At the receiver, demapping from resource elements, decoding, delayer mapping, demodulation and descrambling have to be done by every physical channel. Simulation of these channels is carried out using ModelSim 6.4a and synthesis and implementation are done using PlanAhead 13.4 in Viretx-5 device. Implementation results include Register Transfer Level (RTL) design, power estimation, resource estimation and Field Programmable Gate Array (FPGA) editor.
机译:本文提出了一种具有优化发射器和接收器的长期演进(LTE)下行链路数据信道的组合架构。这项工作主要关注下行链路物理信道,即单输入单输出(SISO),多输入单输出(MISO)和多输入的物理下行共享信道(PDSCH),物理广播信道(PBCH)和物理组播信道(PMCH)。多输出(MIMO)配置。来自高层的数据被加扰,调制,层映射,预编码并映射到发射机中的资源元素。在接收机处,必须由每个物理信道完成对资源元素的解映射,解码,延迟器映射,解调和解扰。这些通道的仿真是使用ModelSim 6.4a进行的,综合和实现是使用Viretx-5设备中的PlanAhead 13.4进行的。实施结果包括寄存器传输级别(RTL)设计,功耗估算,资源估算和现场可编程门阵列(FPGA)编辑器。

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