Process and performance optimization of Triple-RESURF LDMOS with Trenched-Gate

摘要

In this article, we investigate by TCAD simulation, the combination triplereduced surface field (triple-RESURF) and trenched-gate to design an n-type laterallydiffused metal-oxide-semiconductor (LDMOS) transistor with high performance.While similar structures reported in the literature, on the one hand, useeither the triple-RESURF or trenched-gate at once, on the other hand, those featuresrequire at least one additional mask each. We have been able to achieveboth features in one transistor with only eight masks at the front-end of line(FEOL), and one less annealing. Therefore, our proposition will be cheaper andprovide better performance. The structure is obtained by re-organizing the processsteps, re-using other existing masks, and exploiting positive and negativephotoresist photolithography. The resulting specific on-state resistance (R_(ON,SP))is 94 mΩmm~2, and the breakdown voltage (BV) is 71 V. But, most importantly ahigh transconductance (g_m) at high gate voltages, with acceptable off-state leakagecurrent (Ioff), which translates into better RF performance overall than whatis reported in the literature. The maximum oscillation frequency (f_(MAX)) and cutofffrequency (f_T) could reach up to 76 and 43 GHz, respectively. Our device targetsfully integrated IoT ASICs that require power amplifiers.