FPGA implementation of multiphase DPWM generator with phase shedding for DC-DC converters

摘要

The advantages of digital control in power electronics have led to an increasing use of digital pulse width modulators (DPWM). A major focus has been on optimising the DPWM signals and architecture for DC-DC converters to maximise power conversion efficiency and reduce the overall footprint. This paper presents and discusses a dual edge counter-comparator based multiphase DPWM generator with phase-shedding and current sharing functionalities. Phase shedding, or phase dropping, in multiphase power converter is a method that uses turning OFF some of the power converter phases/channels as the load current becomes smaller/lighter in order to improve the lighter load efficiencies. The presented architecture is validated through simulated and experimental test results based off a FPGA implementation of the DPWM generator.