A Web-Based Tool for Learning Digital Circuit High-Level Modeling

摘要

Modeling of increasingly complex digital circuits requires high-level design tools and languages. Design tools based on standard hardware description languages need substantial training which limits their usage in a typical digital system design course. In this paper, we propose a small hardware description language SHDL for circuit modeling and present a novel web-based educational tool. The SHDL includes similar high-level modeling semantics to VHDL but has substantially simplified syntax. The web-based SHDL modeling and simulation tool enables quick introduction to language-based circuit modeling. The SHDL model is automatically translated to the equivalent VHDL model. The proposed tool enables conducting more laboratory and self-learning circuit design experiments important for comprehending the design process. A one-semester laboratory hardware modeling lessons are described and educational experience with the new methodology is discussed.