4-2 compressor of fast booth multiplier for high-speed RISC processor

摘要

A 4-2 compressor for a fast booth multiplier is designed and optimized by two circuits configurations one is constructed of different but optimized XOR circuits with 44 transistors and a total transistor size W/L of 574. The other one is made of single to dual rail transmission gates (TGs) with 56 transistors and a total transistor size W/L of 467. The maximum propagation delay, the power consumption and the chip (layout) area of the two configuration 4-2 circuits are simulated with 0.3 μm and 0.2 μm CMOS process parameters. The results show that the delay and power consumption of circuits with 0.2 μm technology are smaller than those of circuits with 0.3 μm technology. Also, 4-2 circuits are synthesized. This is supported by 0.2 μm CMOS library and design compiler (DC) software (Tools) and compared with the proposed circuits of this research, the designed TG 4-2 compressor is faster and area smaller than that of synthesized one, so the designed TG 4-2 compressors can be optimized for high speed and small chip area applications when compared with the synthesized structures.