Half-clock frequency scheme for counter-based digital pulse-width modulator

摘要

A higher reference clock frequency of counter in counter-based digital pulse-width modulator results in a higher quantisation resolution or higher switching frequency. A half-clock frequency scheme and various implementations of double edge-triggered counter are proposed in this article to cut the reference clock frequency and dynamic power consumption in half while maintaining the quantisation resolution and switching frequency unchanged. In other words, the resolution or switching frequency can be doubled with a prime reference clock frequency. Simulation result proves the feasibility of proposed half-clock frequency scheme and its implementations.