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Teaching hardware description languages to satisfy industry expectations

机译:教授硬件描述语言以满足行业期望

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Industry demands that computer engineers have expertise in FPGA prototyping. A broad knowledge of a hardware description language (HDL) such as Verilog or VHDL is no longer sufficient. Industry expects engineers to write RTL-synthesizable code. Unfortunately, many colleges do not teach this material because the HDL is taught as a secondary topic in a digital design course. That approach does not allow sufficient time to cover efficient coding practices, the use of third-party IP and other essential topics. This paper describes an FPGA prototyping course, based on the Verilog HDL, that is completely separate from any digital design course. The prototyping course is supplemented with FPGA vendor application notes, uses industry-standard EDA tools and fully meets industry expectations.
机译:业界要求计算机工程师具有FPGA原型设计方面的专业知识。对诸如Verilog或VHDL之类的硬件描述语言(HDL)的广泛了解已不再足够。业界期望工程师编写RTL综合代码。不幸的是,由于高密度脂蛋白在数字设计课程中是次要主题,许多大学没有教授这种材料。这种方法没有足够的时间来涵盖有效的编码实践,第三方IP的使用和其他基本主题。本文介绍了基于Verilog HDL的FPGA原型设计课程,该课程与任何数字设计课程完全独立。原型课程补充了FPGA供应商的应用笔记,使用了行业标准的EDA工具,并且完全满足了行业的期望。

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