机译:在时钟周期内实现电源门控架构以降低功耗
Department of Electronics and communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India;
Department of Electronics and communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India;
Department of Electronics and communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India;
Department of Electronics and communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India;
within-clock; architecture; power gating; leakage; isolation;
机译:时钟内功率门控和正常功率门控的混合方法以降低功率
机译:使用时钟门控技术的低功耗精简指令集架构
机译:带门控时钟的低功耗系统VLSI的高级区域/延迟/功率估计
机译:时钟内功率门控架构实施以减少泄漏
机译:功率和定时驱动最佳栅极,时钟缓冲器和时钟线寸在高性能数字集成电路中尺寸
机译:基于超低功耗智能设备的尖峰驱动时钟和功率的始终如一的亚微型尖峰神经网络
机译:使用时钟门控技术的低功耗精简指令集架构