Low-power design of CMOS baseband analog chain for direct conversion receiver

摘要

A low-power CMOS receiver baseband analog (BBA) circuit based on alternating filter and gain stage is reported. For the given specifications of the BBA block, optimum allocation of the gain, input-referred third-order intercept point (IIP3), and noise figure (NF) of each block is performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in 0.18 μm CMOS technology and IIP3 of 30 dBm with a maximum gain of 59 dB and NF of 31 dB are obtained at 3.6 mW power consumption.