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An ultra-thin oxide sub-1 Ⅴ CMOS bandgap voltage reference

机译:超薄氧化亚1ⅤCMOS带隙基准电压源

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This paper presents a sub-1 Ⅴ CMOS bandgap voltage reference that accounts for the presence of direct tunneling-induced gate current. This current increases exponentially with decreasing oxide thickness and is especially prevalent in traditional (non-high-κ∕metal gate) ultra-thin oxide CMOS technologies (t_(ox)<3 nm), where it invalidates the simplifying design assumption of infinite gate resistance. The developed reference (average temperature coefficient, T_(C_AVG), of 22.5 ppm∕℃) overcomes direct tunneling by employing circuit techniques that minimize, balance, and cancel its effects. It is compared to a thick-oxide voltage reference (T_(C_AVG)= 14.0 ppm∕℃) as a means of demonstrating that ultra-thin oxide MOSFETs can achieve performance similar to that of more expensive thick(er) oxide MOSFETs and that they can be used to design the analog component of a mixed-signal system. The reference was investigated in a 65 nm CMOS technology with a nominal V_(DD) of 1 Ⅴ and a physical oxide thickness of 1.25 nm.
机译:本文提出了低于1ⅤCMOS的带隙电压基准,该基准解释了直接隧穿引起的栅极电流的存在。该电流随着氧化物厚度的减小呈指数增长,并且在传统(非高κ∕金属栅极)超薄氧化物CMOS技术(t_(ox)<3 nm)中尤为普遍,从而使无限栅极的简化设计假设无效抵抗性。所开发的参考(平均温度系数T_(C_AVG)为22.5 ppm ∕℃)通过采用最小化,平衡和消除其影响的电路技术克服了直接隧穿问题。它与厚氧化物基准电压(T_(C_AVG)= 14.0 ppm ∕℃)进行比较,以证明超薄氧化物MOSFET可以实现与更昂贵的厚氧化物MOSFET相似的性能,并且可用于设计混合信号系统的模拟组件。在65 nm CMOS技术中对标称进行了研究,标称V_(DD)为1Ⅴ,物理氧化物厚度为1.25 nm。

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