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首页> 外文期刊>International journal of circuit theory and applications >A 1-6 GHz analog radio frequency power driver in 90 nm complementary metal-oxide semiconductor technology for wireless applications
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A 1-6 GHz analog radio frequency power driver in 90 nm complementary metal-oxide semiconductor technology for wireless applications

机译:采用90 nm互补金属氧化物半导体技术的1-6 GHz模拟射频功率驱动器,用于无线应用

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摘要

One of the most challenging subsystems for integrated radio frequency (RF) complementary metal-oxide semiconductor (CMOS) solutions is the power amplifier. A 1-6 GHz RF power driver (RFPD) in 90 nm CMOS technology is presented, which receives signals from on-chip RF signal chain components at -12 dBm power levels and produces a 0 dBm signal to on-chip or off-chip 50 Ω loads. A unique unit cell design is developed for the RFPD to offset issues associated with very wide multi-fingered transistors. The RF driver was fabricated as a stand-alone sub-circuit on a 90 nm CMOS die with other sub-circuits. Experimental tests confirmed that the on-chip RFPD operates up to 6 GHz and is able to drive 50 Ω loads to the desired 0 dBm power level. Spur free dynamic range exceeded 70 dB. The measured power gain was 11.6 dB at 3 GHz. The measured 1 dB compression point and input third-order intercept point (IIP3) were -4.7 dBm and -0.5 dBm, respectively. Also, included are modeling, simulation, and measured results addressing issues associated with interfacing the die to a package with pinouts and the package to a printed circuit test fixture. The simulations were made through direct current (DC), alternating current (AC), and transient analysis with Cadence Analog Design Environment. The stability was also verified on the basis of phase margin simulations from extracted circuit net-lists.
机译:集成射频(RF)互补金属氧化物半导体(CMOS)解决方案最具挑战性的子系统之一是功率放大器。提出了一种采用90 nm CMOS技术的1-6 GHz射频功率驱动器(RFPD),它以-12 dBm的功率水平接收来自片上RF信号链组件的信号,并向片内或片外产生0 dBm信号50Ω负载。针对RFPD开发了独特的单位单元设计,以抵消与非常宽的多指晶体管相关的问题。射频驱动器与其他子电路一起制成90纳米CMOS裸片上的独立子电路。实验测试证实,片上RFPD的工作频率高达6 GHz,并能够将50Ω负载驱动至所需的0 dBm功率电平。无杂散动态范围超过70 dB。在3 GHz处测得的功率增益为11.6 dB。测得的1 dB压缩点和输入三阶交调点(IIP3)分别为-4.7 dBm和-0.5 dBm。此外,还提供了建模,仿真和测量结果,解决了与管芯与带有引脚分配的封装接口以及封装与印刷电路测试夹具的接口相关的问题。通过直流(DC),交流(AC)以及Cadence Analog Design Environment的瞬态分析进行了仿真。稳定性还基于从提取的电路网表进行的相位裕度模拟进行了验证。

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