Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design

摘要

Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Although Boolean multipliers have natural power-awareness to the changing of input precision, deeply pipelined designs do not have this benefit. A two-dimensional pipeline gating scheme is proposed in this paper to improve the power-awareness in these designs. This technique is to gate the clock to registers in both vertical direction (data flow direction in pipeline) and horizontal direction (within each pipeline stage). For signed multipliers using 2's complement representation, sign extension, which wastes power and causes longer delay, could be avoided by implementing this technique. Very little additional area is needed so that the overhead is hardly noticeable. Simulation results show that an average power saving of 65-66% and latency reduction of 44-47% can be achieved for multipliers under equal input precision probabilities. An application of power-aware multipliers on FIR design is also included.