Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure

摘要

The authors describe the design, integration and characterisation of a bit-level pipelined self-timed multiplier architecture. The differential structure SODS (switched-output differential structure) has been used for computation blocks and the PLCAR structure (protocol and latching controlled by acknowledge and request) for the interface blocks, introduced in an array-based architecture. A 4/spl times/4-bit multiplier has been integrated in a 1.0 /spl mu/m CMOS technology and the proposed architecture has been compared with other asynchronous approaches, showing a considerable improvement, up to 50%, in terms of area, speed and power consumption. Compared with a synchronous approach, the main advantage of the proposed architecture is a lower power consumption below a certain incoming input data rate, but at the expense of area and speed.