On the Accuracy of Digital Phase Sensitive Detectors Implemented in FPGA Technology

摘要

This paper investigates the possible causes of inaccuracy in a phase measurement system implemented using a digital lock-in amplifier architecture and built using FPGA technology. All contributions to the overall inaccuracy of the measurement are discussed and calculated or, when exact calculations cannot be made, their impact is carefully estimated. The theoretically derived worst case inaccuracies are compared with practical measurement results. This paper concludes that when phase measurement systems are used with signals with a low signal-to-noise ratio (SNR), the low-pass filter in the lock-in amplifier plays a critical role in the overall accuracy of the system whereas for applications with a high SNR the analog to digital converter is the major contributor to the overall measurement inaccuracy.