Analog-Assisted Digital Capacitorless Low-Dropout Regulator Supporting Wide Load Range

摘要

Capacitorless (CL) low-dropout regulators (LDO) have gained significant research interest for point-of-load voltage regulation without off-chip capacitors. While analog CL-LDOs can deliver superior power supply rejection (PSR), digital CL-LDOs are more scalable and efficient. To achieve the advantages of both types, this paper presents a digital CL-LDO with an analog PSR enhancer, delivering strong PSR without compromising scalability and efficiency. Load regulation is performed by an asynchronous digital feedback controller for fast transient response and scalable load drivability. PSR is achieved by a load-insensitive wide-bandwidth analog controller. A prototype chip of the analog-assisted digital CL-LDO is fabricated in a 130-nm CMOS process with an active area of 0.0645 mm^{2, supporting load current up to 50 mA at nominal 1-V input and 0.8-V output. The measured PSR is better than -20 dB for frequencies up to 10 MHz, and the measured current efficiency peaks at 99.3%, with average current efficiency of 96.7% across 50× load range. The measured transient response to a full load step, with two values of load capacitance (100 pF and 10 nF), demonstrates the LDO's stable operation over a wide range of load resistance and capacitance.}