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A Novel Application of Verilog-A to Modeling and simulation of High-Speed Interconnects in time/Frequency Transform-Domain

机译:Verilog-A在时间/频率变换域中的高速互连建模和仿真中的新应用

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摘要

This letter presents a novel application of the Verilog-A, which is a hardware description language for analog Circuits, to the modeling and simulation of high-speed intercon- Nects in time/frequency transform-domain for signal integrity Problems. This modeling method with the Verilog-A language Would handle the transfer function approximation and admit- Tance matrices, which are expressed by the dominant poles and Residues as used in AWE technique. Finally, it is shown that Modeling and simulation of the high-speed interconnects with Nonlinear terminations can be done easily.
机译:这封信提出了Verilog-A(一种用于模拟电路的硬件描述语言)在时/频变换域中用于信号完整性问题的高速互连的建模和仿真的新应用。这种使用Verilog-A语言的建模方法将处理传递函数近似和导纳矩阵,这些矩阵由AWE技术中使用的主导极点和残基表示。最后,表明可以轻松地完成带有非线性终端的高速互连的建模和仿真。

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