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首页> 外文期刊>IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences >A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI
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A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI

机译:基于双电源电压技术的新型PD-SOI布局方法

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摘要

This paper presents a novel layout approach using dual supply voltage technique. In Placing and Routing (P&R) phase, conventional approaches for dual supply voltages need to separate low supply voltage cells from high voltage ones. Consequently its layout tends to be complex compared with single supply voltage layout. Our layout approach uses cells having two supply voltage rails. Making these cells is difficult in bulk due to increase in area by n-well isolation or in delay by negative body bias caused by sharing n-well. On the other hand, making cells with two supply voltage rails is easy in body-tied PD-SOI owing to trench isolation of each body of transistor. Since our approach for dual supply voltages offers freedom for placement as much as conventional ones for single supply voltage, exsting P&R tools can be used without special operation. Simulation results with MCNC circuits and adders show that our approach reduces power by 23% and 25%, respectively, showing almost the same delay with single supply voltage layout.
机译:本文提出了一种使用双电源电压技术的新颖布局方法。在放置和布线(P&R)阶段,用于双电源电压的常规方法需要将低电源电压单元与高电压单元分开。因此,与单电源电压布局相比,其布局趋于复杂。我们的布局方法使用具有两个电源电压轨的单元。由于通过n阱隔离增加面积或由于共享n阱导致的负体偏向导致的延迟,使得制造这些电池非常困难。另一方面,由于晶体管的每个主体的沟槽隔离,在体式PD-SOI中易于制造具有两个电源电压轨的单元。由于我们的双电源电压方法提供了与传统的单电源电压一样多的放置自由度,因此无需特殊操作即可使用现有的P&R工具。 MCNC电路和加法器的仿真结果表明,我们的方法分别将功率降低了23%和25%,在单电源电压布局下显示出几乎相同的延迟。

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