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首页> 外文期刊>IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences >An Analysis of Frame Synchronization Systems with Racing Counters and Majority Rule for M-ary/SS Communication Systems
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An Analysis of Frame Synchronization Systems with Racing Counters and Majority Rule for M-ary/SS Communication Systems

机译:M-ary / SS通信系统中带有竞速计数器和多数规则的帧同步系统分析

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摘要

In this paper, a simple frame synchronization system for M-ary Spread Spectrum (M-ary/SS) communication systems is analyzed, In particular, synchronization performance, bit error rate performance, and Spread Spectrum Multiple Access (SSMA) performance are analyzed. The frame synchronization system uses the racing counters. The transmitted signal contains framing chips that are added to spreading sequences. In the receiver, the framing chips are detected from several frames. The authors have proposed the simple frame synchronization system that detects framing chips from consecutive 2 frames. In this system, as the number of framing chips increases, synchronization performance improves and bit error rate performance degrades. In this paper a frame synchronization system that improves bit error rate performance is treated and analyzed. As the result, when the number of reference frames is 3, the bit error rate is much improved than the conventional system.
机译:本文分析了一种简单的用于M元扩频(Mary / SS)通信系统的帧同步系统,尤其是分析了同步性能,误码率性能和扩频多址(SSMA)性能。帧同步系统使用赛车计数器。传输的信号包含成帧码片,这些成帧码片被添加到扩频序列中。在接收机中,从几个帧中检测出成帧码片。作者提出了一种简单的帧同步系统,该系统可从连续的2个帧中检测成帧码片。在该系统中,随着成帧芯片数量的增加,同步性能提高,而误码率性能下降。本文研究并分析了一种可提高误码率性能的帧同步系统。结果,当参考帧的数量为3时,与传统系统相比,误码率大大提高。

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